The Turbo Processor
A hardware CPU written in SystemVerilog that executes Turbo binaries identically to the software simulator. Single-cycle and 5-stage pipelined datapaths with full data forwarding and hazard detection.
Architecture
Two Implementations, One ISA
Both variants implement the entire 32-bit Turbo ISA with identical results. The pipeline trades single-cycle simplicity for higher clock frequencies.
Single-Cycle
Every instruction completes in exactly one clock cycle. The critical path spans IMEM → Decode → RegRead → ALU → DMEM → Writeback, limiting max frequency but providing a simple, verifiable baseline.
5-Stage Pipeline
Breaks execution into IF, ID, EX, MEM, and WB stages. Features EX→EX and MEM→EX data forwarding, load-use stalls, and predict-not-taken branch flushing with a 2-cycle penalty.
Pipeline Stages
Data Execution Flow
IF
Instruction Fetch
PC → IMEM
ID
Decode & Read
Control + RegFile
EX
Execute
ALU + Branch
MEM
Memory
DMEM R/W
WB
Writeback
Result → RegFile
Execution Forwarding
When EX/MEM holds a value destined for the Register File and the ID/EX stage needs it immediately, the ex_mem_result is multiplexed directly into the ALU input. Highest priority.
Memory Forwarding
If data loaded from memory is needed in the next instruction's EX phase, a 1-cycle stall bubble is inserted, then mem_wb_data is forwarded to the ALU.
RTL Modules
SystemVerilog Components
ALU
Combinational arithmetic/logic unit with ADD, SUB, MUL, AND, OR, XOR, SHL, SHR, ASHR, SLT, and NOT operations. Outputs zero and negative flags.
Control Unit
Decodes 6-bit opcode into reg_write, mem_read, mem_write, alu_op, branch, jump, link, lui, and halt control signals.
Register File
16 × 32-bit register file with 2 read ports and 1 synchronous write port. r0 is hardwired to zero.
Memory
Parameterized word-addressed memory primitive with optional init file. Used for both instruction and data memory instances.
Program Counter
PC register with enable-gated next-PC selection: sequential (PC+4), branch target, jump target, or register indirect.
Forwarding Unit
Detects RAW hazards and selects forwarded operands. EX/MEM forwarding has priority over MEM/WB. Never forwards writes to r0.
Hazard Unit
Handles load-use stalls (1-cycle bubble, PC and IF/ID frozen) and control-hazard flushes (predict-not-taken, 2-cycle penalty).
Datapath
Single-Cycle Signal Flow
Writeback MUX Rules
linkPC + 4JAL saves return addressluiimm << 14LUI loads upper immediatememdmem_rdataLOAD reads data memoryelseexec_resALU / DIV / MOD result
Execution Profile
In single-cycle execution, the ALU, DIV/MOD modules, and sign-extension blocks evaluate continuously in parallel. The Control Unit orchestrates final writeback selection via multiplexers at the end of the clock cycle.